JPH0339352B2 - - Google Patents

Info

Publication number
JPH0339352B2
JPH0339352B2 JP57186838A JP18683882A JPH0339352B2 JP H0339352 B2 JPH0339352 B2 JP H0339352B2 JP 57186838 A JP57186838 A JP 57186838A JP 18683882 A JP18683882 A JP 18683882A JP H0339352 B2 JPH0339352 B2 JP H0339352B2
Authority
JP
Japan
Prior art keywords
signal
digital information
output
frequency
read clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57186838A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5977605A (ja
Inventor
Takaaki Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansui Electric Co Ltd
Original Assignee
Sansui Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansui Electric Co Ltd filed Critical Sansui Electric Co Ltd
Priority to JP57186838A priority Critical patent/JPS5977605A/ja
Priority to US06/545,290 priority patent/US4580278A/en
Publication of JPS5977605A publication Critical patent/JPS5977605A/ja
Publication of JPH0339352B2 publication Critical patent/JPH0339352B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP57186838A 1982-10-26 1982-10-26 読取りクロツク生成方式 Granted JPS5977605A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57186838A JPS5977605A (ja) 1982-10-26 1982-10-26 読取りクロツク生成方式
US06/545,290 US4580278A (en) 1982-10-26 1983-10-25 Read clock producing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57186838A JPS5977605A (ja) 1982-10-26 1982-10-26 読取りクロツク生成方式

Publications (2)

Publication Number Publication Date
JPS5977605A JPS5977605A (ja) 1984-05-04
JPH0339352B2 true JPH0339352B2 (en]) 1991-06-13

Family

ID=16195510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57186838A Granted JPS5977605A (ja) 1982-10-26 1982-10-26 読取りクロツク生成方式

Country Status (2)

Country Link
US (1) US4580278A (en])
JP (1) JPS5977605A (en])

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173677A (ja) * 1986-01-28 1987-07-30 Mitsubishi Electric Corp 記憶装置
US4789838A (en) * 1987-03-23 1988-12-06 Cheng Jyi Min Pulse detection circuit using amplitude and time qualification
JPH0414652Y2 (en]) * 1987-05-13 1992-04-02
US4949360A (en) * 1989-08-08 1990-08-14 International Business Machines Corporation Synchronizing circuit
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5204848A (en) * 1991-06-17 1993-04-20 International Business Machines Corporation Adjusting amplitude detection threshold by feeding back timing-data phase errors
JP2807362B2 (ja) * 1991-09-30 1998-10-08 株式会社東芝 情報再生装置
US5867332A (en) * 1992-06-22 1999-02-02 Fujitsu Limited Window margining apparatus with delayed read data single shot (DRDSS) circuit for adjustably delaying a data pulse reproduced from a data storage device
US5570243A (en) * 1993-06-22 1996-10-29 Fujitsu Limited Variable delay circuit including current mirror and ramp generator circuits for use in the read channel of a data storage device
US5892631A (en) * 1995-09-08 1999-04-06 Seagate Technology, Inc. Method and an arrangement for detecting state transitions in a read signal during a bit cell timing window
JP3179429B2 (ja) * 1999-01-29 2001-06-25 日本電気アイシーマイコンシステム株式会社 周波数測定用テスト回路及びそれを備えた半導体集積回路
US6369967B1 (en) * 2000-07-11 2002-04-09 Marvell International, Ltd. Phase-adjustment of divided clock in disk head read circuit
FR2880482B1 (fr) * 2004-12-30 2007-04-27 Cit Alcatel Dispositif de conversion d'un signal transmis en un signal numerique
JP5407270B2 (ja) * 2008-10-22 2014-02-05 日本電気株式会社 受信回路、電子機器、及び受信回路の制御方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736581A (en) * 1971-07-02 1973-05-29 Honeywell Inc High density digital recording
US3755748A (en) * 1972-03-06 1973-08-28 Motorola Inc Digital phase shifter/synchronizer and method of shifting
JPS5081715A (en]) * 1973-11-23 1975-07-02
JPS5580867A (en) * 1978-12-12 1980-06-18 Sony Corp Block synchronous signal extracting circuit

Also Published As

Publication number Publication date
US4580278A (en) 1986-04-01
JPS5977605A (ja) 1984-05-04

Similar Documents

Publication Publication Date Title
CA1070395A (en) Versatile phase-locked loop phase detector
JPH0339352B2 (en])
KR900001593B1 (ko) 디지탈신호 재생회로
JP3345515B2 (ja) ピークシフト補正回路およびそれを使用した磁気記録媒体再生装置
JP2999508B2 (ja) 時間軸誤差信号発生装置
US4580100A (en) Phase locked loop clock recovery circuit for data reproducing apparatus
US3656149A (en) Three frequency data separator
KR960035239A (ko) 디코드장치 및 기억장치
JPS59167813A (ja) 位相同期回路
JPH01133269A (ja) アナログフロッピーディスクデータセパレータ
JPS6260747B2 (en])
JPH0879059A (ja) 基準クロック発生回路
JPH04345967A (ja) 同期データ取り込み方法および回路
JP2675096B2 (ja) 再生信号補正方法
JPH0877503A (ja) ピーク検出回路およびそれを使用した記録媒体再生装置
JPH0247653Y2 (en])
JPH0249573B2 (en])
JPS6155824B2 (en])
JPS6285513A (ja) スライスレベル自動設定回路
JPH028385B2 (en])
JP2659999B2 (ja) ヘリカルスキャン方式のテープ再生装置
JPH0743890B2 (ja) デイジタル信号伝送装置
JPH0834039B2 (ja) ディジタル信号処理装置
JPH07201137A (ja) 位相同期ループのロック検出方法及びロック検出装置
JPH0211048B2 (en])